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S3C44B0X01-EDR0-아이씨뱅큐
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S3C44B0X01-EDR0

ARM7TDMI, 통신용으로 디자인되어있음, 2xHDLC, 2xUART, 160핀 QFP패키지

소비자가 견적문의요망
적립금 160
제조사 Samsung Electronics
상품코드 P000073458
배송기간 입금 확인 후 4일~6일
재고위치 해외 지사
구매수량
pcb-아이씨뱅큐
S3C44B0X01-EDR0 - ARM7TDMI, 통신용으로 디자인되어있음, 2xHDLC, 2xUART, 160핀 QFP패키지

S3C44B0X01-EDR0



Features

 

Architecture

● Integrated system for hand-held devices and general embedded applications.

● 16/32-Bit RISC architecture and powerful instruction set with ARM7TDMI CPU core.

● Thumb de-compressor maximizes code density while maintaining performance.

● On-chip ICEbreaker debug support with JTAGbased debugging solution.

● 32x8 bit hardware multiplier.

● New bus architecture to implement Low-Power SAMBA II(SAMSUNG's ARM CPU embedded Micro-controller Bus Architecture).

System Manager

● Little/Big endian support.

● Address space: 32Mbytes per each bank. (Total 256Mbyte)

● Supports programmable 8/16/32-bit data bus width for each bank.

● Fixed bank start address and programmable bank size for 7 banks.

● Programmable bank start address and bank size for one bank.

● 8 memory banks.

- 6 memory banks for ROM, SRAM etc.

- 2 memory banks for ROM/SRAM/DRAM(Fast Page, EDO, and Synchronous DRAM)

● Fully Programmable access cycles for all memory banks.

● Supports external wait signal to expend the bus cycle.

● Supports self-refresh mode in DRAM/SDRAM for power-down.

● Supports asymmetric/symmetric address of DRAM.

Cache Memory & internal SRAM

● 4-way set associative ID(Unified)-cache with 8Kbyte.

● The 0/4/8 Kbytes internal SRAM using unused cache memory.

● Pseudo LRU(Least Recently Used) Replace Algorithm.

● Write through policy to maintain the coherence between main memory and cache content.

● Write buffer with four depth.

● Request data first fill technique when cache miss occurs.

Clock & Power Manager

● Low power

● The on-chip PLL makes the clock for operating MCU at maximum 66MHz.

● Clock can be fed selectively to each function block by software.

● Power mode: Normal, Slow, Idle and Stop mode.

Normal mode: Normal operating mode.

Slow mode: Low frequency clock without PLL

Idle mode: Stop the clock for only CPU

Stop mode: All clocks are stopped

● Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode.

Interrupt Controller

● 30 Interrupt sources

( Watch-dog timer, 6 Timer, 6 UART, 8 External interrupts, 4 DMA , 2 RTC, 1 ADC, 1 IIC, 1 SIO )

● Vectored IRQ interrupt mode to reduce interrupt latency.

● Level/edge mode on the external interrupt sources

● Programmable polarity of edge and level

● Supports FIQ (Fast Interrupt request) for very urgent interrupt request

Timer with PWM (Pulse Width Modulation)

● 5-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation

● Programmable duty cycle, frequency, and polarity

● Dead-zone generation.

● Supports external clock source.

RTC (Real Time Clock)

● Full clock feature: msec, sec, min, hour, day, week, month, year.

● 32.768 KHz operation.

● Alarm interrupt for CPU wake-up.

● Time tick interrupt

General purpose input/output ports

● 8 external interrupt ports

● 71 multiplexed input/output ports

UART

● 2-channel UART with DMA-based or interruptbased operation

● Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive

● Supports H/W handshaking during transmit/receive

● Programmable baud rate

● Supports IrDA 1.0 (115.2kbps)

● Loop back mode for testing

● Each channel have two internal 32-byte FIFO for Rx and Tx.

DMA Controller

● 2 channel general purpose Direct Memory Access controller without CPU intervention.

● 2 channel Bridge DMA (peripheral DMA) controller.

● Support IO to memory, memory to IO, IO to IO with the Bridge DMA which has 6 type's DMA

requestor: Software, 4 internal function blocks

(UART, SIO, Timer, IIS), and External pins.

● Programmable priority order between DMAs (fixed or round-robin mode)

● Burst transfer mode to enhance the transfer rate on the FPDRAM, EDODRAM and SDRAM.

● Supports fly-by mode on the memory to external device and external device to memory transfer mode

A/D Converter

● 8-ch multiplexed ADC.

● Max. 100KSPS/10-bit.

LCD Controller

● Supports color/monochrome/gray LCD panel

● Supports single scan and dual scan displays

● Supports virtual screen function

● System memory is used as display memory

● Dedicated DMA for fetching image data from

system memory

● Programmable screen size

● Gray level: 16 gray levels

● 256 Color levels

Watchdog Timer

● 16-bit Watchdog Timer

● Interrupt request or system reset at time-out IIC-BUS Interface

● 1-ch Multi-Master IIC-Bus with interrupt-based operation.

● Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode or up to 400 Kbit/s in the fast mode.

IIS-BUS Interface

● 1-ch IIS-bus for audio interface with DMA-based

operation.

● Serial, 8/16bit per channel data transfers

● Supports MSB-justified data format

SIO (Synchronous Serial I/O)

● 1-ch SIO with DMA-based or interrupt -based operation.

● Programmable baud rates.

● Supports serial data transmit/receive operations 8-bit in SIO.

Operating Voltage Range

● Core : 2.5V I/O : 3.0 V to 3.6 V

Operating Frequency

● Up to 66 MHz

Package

● 160 LQFP / 160 FBGA

 

 

Application

 

 

 

 

Maximun Ratings

 

 

 

 

Package/Demension

 

 

 

 

Ordering Information

 




 
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